There is an interest in the development of flexible circuitry for use in a range of devices, including electro-optical arrays and display panels. Proposed solutions for fabricating thin-film transistor (TFT) devices, used in switching and driver circuitry, onto flexible metallic and plastic substrates have not yet met with commercial success, however.
Conventionally, TFT devices have been fabricated on rigid substrates, typically glass or silicon, using a well-known sequence of deposition, patterning and etching steps. For example, amorphous silicon TFT devices require deposition, patterning, and etching of metals, such as aluminum, chromium or molybdenum; of amorphous silicon semiconductors; and of insulators, such as SiO2 or Si3N4, onto a substrate. The semiconductor thin film is formed in layers having typical thicknesses ranging from several nanometers (nm) to several hundred nm, with intermediary layers having thicknesses on the order of a few microns, and may be formed over an insulating surface that lies atop the rigid substrate.
The requirement for a rigid substrate has been based largely on the demands of the fabrication process itself. Rigidity allows the fabrication system to more accurately register the substrate in position for the different process steps. Thermal characteristics are also particularly relevant. TFT devices are fabricated at relatively high temperatures, making it difficult to work with many types of plastics and with some metals, due to thermal expansion characteristics. Thus far, the range of substrate materials that have been used successfully is somewhat limited, generally to glass, quartz, or other rigid, silicon-based materials.
TFT devices have been successfully formed on some types of metal foil and plastic substrates, indicating that there is at least some measure of flexibility that can be allowed for their fabrication. However, inherent problems include material incompatibility between the substrate and TFT materials, thermal expansion mismatch between substrate and device layers, and difficulties with planarity or smoothness and surface morphology. It is desirable to have these problems satisfactorily resolved in order to make commercialization a reality.
The fabrication process for the TFT can require temperatures typically in the range of 125-300 degrees C. or higher, including temperatures at levels where many types of plastic substrates would be unusable. Thus, it is widely held, as is stated in U.S. Pat. No. 7,045,442 (Maruyama et al.), that a TFT cannot be directly formed on a plastic substrate.
U.S. Pat. No. 6,492,026 (Graffet al.) discloses the use of flexible plastic substrates having relatively high glass transition temperatures Tg, typically above 120 degrees C. However, the capability for these substrates to withstand conventional TFT fabrication temperatures much above this range is questionable. Moreover, in order to use these plastics, considerable effort is expended in protecting the substrate and the device(s) formed from scratch damage and moisture permeation, such as using multiple barrier layers. The use of high-performance plastics, as is noted in the Graff et al. '026 disclosure, still leaves thermal expansion difficulties (expressed using Coefficient of Thermal Expansion, CTE). Solutions of this type generally require additional planarization and isolation layers and processes in order to protect the plastic.
One problem relates to surface quality of the substrate, also termed planarity. TFT fabrication requires that the substrate surface be extremely smooth, with no more than about 50 nm peak-to-peak roughness. However, this level of smoothness is extremely difficult to achieve without special tooling or other processing of the plastic. Even methods such as spin coating or other deposition techniques are not able to achieve smoothness at this level repeatably and at low cost.
U.S. Patent Application Publication No. 2007/0091062 entitled “Active Matrix Displays and Other Electronic Devices Having Plastic Substrates” by French et al. describes forming a flexible substrate by first depositing substrate material onto a glass carrier plate, with an optional release layer between them. Then, once the substrate thickness is achieved, the exposed substrate surface can be treated for planarization, such as by adding one or more additional layers, and circuit components such as TFT arrays can be fabricated thereon. At the end of the component fabrication process, the substrate and its circuitry are then removable from the glass carrier, such as using a laser release process.
With methods such as those disclosed in the US 2007/0091062 French et al. application, care is taken to provide a smooth and uniform surface, using deposition methods such as spin coating, skiving with a blade, or various printing techniques. However, even with the use of spin coating and other highly precise deposition methods, the surface of the deposited substrate may still need further treatment steps to improve planarization before circuit lay-down can begin. This adds complexity and cost to the electronic device fabrication process. Moreover, conventional solutions are directed to smoothing the surface and there can be applications where it is useful not only to provide surface smoothness, but also to provide one or more relief features in the substrate.
Various techniques for supporting a flexible substrate on a carrier have been developed. For example, reference is made to U.S. Patent Application 2008/0026581 (Ser. No. 11/461,080) filed Jul. 31, 2006 by Tredwell et al. entitled FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES FORMED THEREON; and U.S. Patent Application 2008/0090338 (Ser. No. 11/538,173) filed Oct. 3, 2006 by Tredwell et al. entitled FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES AND TRACES. The disclosure of each of these applications is incorporated by reference into the present specification.
Thus, it can be seen that although there has been interest in developing and expanding the use of plastics as flexible substrates, there is still a need for extra steps in surface treatment, such as planarization.